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1024点高速FFT处理器的FPGA设计与实现
引用本文:王文芳,周盛,王晓春,王立伟,计建军,杨军,王延群.1024点高速FFT处理器的FPGA设计与实现[J].国际生物医学工程杂志,2011,34(4):205-208.
作者姓名:王文芳  周盛  王晓春  王立伟  计建军  杨军  王延群
作者单位:中国医学科学院北京协和医学院生物医学工程研究所, 天津,300192
基金项目:协和青年科研基金;中央级公益性科研院所基本科研业务专项
摘    要:目的 设计满足高速实时信号处理需要的快速傅里叶变换(FFT)处理器。方法采取基-2按频率抽取( DIF)FFT算法,蝶形运算单元采用流水线方式,接收数据采用乒乓操作的方法设计基于现场可编程门阵列(FPGA)的1 024点、32位字长、定点复数FFT处理器。结果在时钟100 MHz下,计算1次1 024点定点FFT耗时约...

关 键 词:现场可编程  门阵列  1  024点快速傅里叶变换  蝶形运算  乒乓操作

Design and realization of 1024-point high-speed FFT processor based on FPGA
WANG Wen-fang,ZHOU Sheng,WANG Xiao-chun,WANG Li-wei,JI Jian-jun,YANG Jun,WANG Yan-qun.Design and realization of 1024-point high-speed FFT processor based on FPGA[J].International Journal of Biomedical Engineering,2011,34(4):205-208.
Authors:WANG Wen-fang  ZHOU Sheng  WANG Xiao-chun  WANG Li-wei  JI Jian-jun  YANG Jun  WANG Yan-qun
Institution:. (Institute of Biomedical Engineering, Chinese Academy of Medical Sciences & Peking Union Medical College, Tianjin 300192, China)
Abstract:Objective To design a fast fourier transform (FFT) processor to meet the needs for high-speed and real-time signal processing. Methods A 1 024-point, 32-bit, fixed, complex FFT processor was designed based on field programmable gate array (FPGA) by using radix-2 decimation in frequency(DIF) algorithm and pipeline structure in the butterfly module and ping-pong operation in data storage unit. Results When the primary clock was 100 MHz, 1 024-point FFT calculation took about 62.95us. The processor was fast enough for processing highspeed and real-time signals. Conclusion The results provides reference value that theoretical study of the FFT algorithm can be applied in the adaptive dynamic filter of ultrasonic diagnostic system and ultrasonic doppler flow measurement system.
Keywords:Field programmable gate array  1 024-point FFT  Butterfly  Ping-pong operation
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