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一种用于功能磁共振的同步器
引用本文:眭建锋,梁振,胡孝朋,周小强,何珊,陈月明,何文胜.一种用于功能磁共振的同步器[J].北京生物医学工程,2014,33(4):393-396.
作者姓名:眭建锋  梁振  胡孝朋  周小强  何珊  陈月明  何文胜
作者单位:安徽医科大学生命科学学院生物医学工程系,合肥,230032;安徽医科大学第一附属医院放射科,合肥,230032
基金项目:安徽省高等学校省级优秀青年人才基金项目(项目编号:2012SQRL068ZD)安徽省自然科学基金资助项目(项目编号:1308085QC55)安徽医科大学校科学研究基金项目(项目编号:2011xkj012)
摘    要:目的 功能磁共振(functional magnetic resonance imaging,fMRI)在采集图像数据时,有两种同步信号输出方式:其一,每采集一层图像输出一个同步信号;其二,采集一幅脑图输出一个同步信号.由于第一种输出方式中同步信号过于密集,导致刺激计算机无法及时记录同步信号,从而失去同步.为此本文设计出一种基于复杂可编程逻辑器件(complex programmable logic devices,CPLD)的单参数(同步参数)同步器.方法 采集一幅脑图时,该同步器对第一种同步信号的上升沿进行计数,计数期间输出维持高电平,直到最后一个同步信号到来,才把输出拉低为低电平,从而实现第一种同步信号到第二种同步信号的转换.然后用Quartus 9.1对信号转换进行仿真以验证其功能.结果 经过CPLD处理器后,第一种同步信号被处理成第二种同步信号.此外,基于本设计做出的同步器亦成功应用于GE Sigma3.0T.结论 本文设计了具有同步信号转换能力的同步器,成功实现了输出方式的转变.该同步器达到同步信号转换要求,并具有较好的兼容性.

关 键 词:功能磁共振  同步  复杂可编程逻辑器件  兼容性

A synchronizer used for fMRI
Institution:SUI Jianfeng, LIANG Zhen, HU Xiaopeng, ZHOU Xiaoqiang , HE Shan, CHEN Yueming, HE Wensheng(1 Department of Biomedical Engineering, College of Life Science, Anhui Medical University, Hefei 230032; 2 Department of Radiology, the First Affiliated Hospital of Anhui Medical University, Hefei 230032)
Abstract:Objective Synchronization signal has two output types in the acquisition of the image data by functional magnetic resonance imaging (fMRI). One type is that a synchronization signal is outputted after acquiring each layer image. The other type is that a synchronization signal is outputted after acquiring a whole brain map. However, for the first type of synchronization signal, there is a loss of synchronization because the synchronization signal is too dense to be recorded in time by the stimuli-controlled computer. Therefore, in this paper a single parameter (synchronous parameter) synchronizer is designed based on CPLD. Methods The synchronizer counts the positive edge of the first type of synchronization signal in the acquisition of a brain map. Meanwhile, the output of the synchronizer remains high level and will not be pulled down to low level during the counting period until the last synchronization signal is coming. The synchronizer achieves the translation of the synchronous signal from the first type into the second type. Then we simulate the signal conversion by Quartus 9.1 to verify its functionality. Results The first synchronization signal is processed into the second synchronization signal through the CPLD processor. In addition, the synchronizer based on this design is also successfully applied to GE Sigma 3.0T. Conclusions This research designs a synchronizer which has conversion
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